In recent years, a semiconductor memory device capable of a so-called interleaving operation has been proposed in order to speed up access to cache memory. An interleaving operation is an operation that divides a memory cell array into multiple areas, and provides a cache memory, a decoder, and so on to each of those multiple areas to enable parallel operation of the multiple areas, thereby allowing operation of the memory device to be speeded up.
However, there is a problem that in a semiconductor memory device adopting such an interleaving operation, rescue efficiency in a redundancy system deteriorates compared to when such an interleaving operation is not adopted.